CASPER’s DSP Development Documentation

Contained herein is the documentation for the HDL IP cores maintained by the CASPER community. These may be pulled into mlib_devel toolflow by pointing the HDL_DSP_DEVEL_PATH environment variable to the cloned casper_dspdevel repository.

IP Cores:

• Accumulator Library
  • Purpose
    • Addr Bram Vacc
      • Ports
      • Parameters
    • Simple Bram Vacc
      • Ports
      • Parameters
    • DSP48e BRAM VACC
      • Ports
      • Parameters
• Delays Library
  • Purpose
    • Bram Delay
      • Ports
      • Parameters
    • Bram Delay En Plus
      • Ports
      • Parameters
    • Bram Delay Prog
      • Ports
      • Parameters
    • Bram Delay Prog DP
      • Ports
      • Parameters
    • Delay Sync
      • Ports
      • Parameters
    • Window Delay
      • Ports
      • Parameters
    • Pipeline
      • Ports
      • Parameters
• Flow Control Library
  • Purpose
    • Bus Create
      • Ports
      • Parameters
    • Bus Expand
      • Ports
      • Parameters
    • Munge
      • Ports
      • Parameters
• Misc Library
  • Purpose
    • Bit Reverse
      • Ports
      • Parameters
    • Edge Detect
      • Ports
      • Parameters
    • Armed Trigger
      • Ports
    • Pulse Extender
      • Ports
      • Parameters
    • Real/Imaginary to Complex
      • Ports
      • Parameters
    • Complex to Real/Imaginary
      • Ports
      • Parameters
    • Complex to Real/Imaginary
      • Ports
      • Parameters
    • Freeze Counter
      • Ports
      • Parameters
    • Stopwatch
      • Ports
    • Triggered Counter
      • Ports
      • Parameters
    • Power
      • Ports
      • Parameters
    • Complex Add Sub
      • Ports
      • Parameters
    • Convert
      • Ports
      • Parameters
    • Conv
      • Ports
• R2SDF FFT
• Reorder Library
  • Purpose
    • Barrel Switcher
      • Ports
      • Parameters
    • Square Transposer
      • Ports
      • Parameters
    • Reorder
      • Ports
      • Parameters
• Wideband FFT
  • Purpose
  • Module Overview
  • Firmware Interface
    • Clock Domains
    • Interface signals
      • Complex FFT
      • Two Real FFT’s
      • Remarks
    • Parameters
      • FFT parameters
      • Data parameters
      • Synth/Imp Parameters
  • Module Architecture
    • fft_r2_pipe
    • fft_r2_par
    • fft_r2_wide
    • Quantisation
• Wideband PFB
  • Purpose
  • Module Overview
  • Firmware Interface
    • Clock Domains
    • Interface signals
    • Parameters
      • PFB parameters

Indices and tables

• Index

• Module Index

• Search Page