####################
Flow Control Library
####################
.. _flowcontrol:

*******
Purpose
*******
.. _flowcontrol_purpose:

The flow-control library contains all casper_flow_control HDL modules wrapped for Simulink.
These blocks provide combinatorial entities to redirect standard logic-vectors.

===========
Bus Create
===========
Concatenates many input bus to create a unified output bus.

-----
Ports
-----
+-------------+-----------------+------------+-------------------------------------------------+
| Signal      | Type            | Size       | Description                                     |
+=============+=================+============+=================================================+
| din_0...    | std_logic_vector| any        | The input vectors                               |
+-------------+-----------------+------------+-------------------------------------------------+
| dout        | std_logic_vector| any        | The output vector                               |  
+-------------+-----------------+------------+-------------------------------------------------+

----------
Parameters
----------
+---------------------+------------------+----------+------------------------------------------------------------+
| Generic             | Type             | Value    | Description                                                |
+=====================+==================+==========+============================================================+
| Input Bit Widths    | Comma-delimited  | 4,1,2,1  | The bit-width of each input vector                         |
|                     | Integers         |          |                                                            |
+---------------------+------------------+----------+------------------------------------------------------------+

===========
Bus Expand
===========
Breaks the input bus out into many smaller, constituent output buses.

-----
Ports
-----
+-------------+-----------------+------------+-------------------------------------------------+
| Signal      | Type            | Size       | Description                                     |
+=============+=================+============+=================================================+
| din         | std_logic_vector| any        | The input vector                                |
+-------------+-----------------+------------+-------------------------------------------------+
| dout_0...   | std_logic_vector| any        | The output vectors                              |  
+-------------+-----------------+------------+-------------------------------------------------+

----------
Parameters
----------
+---------------------+------------------+----------+------------------------------------------------------------+
| Generic             | Type             | Value    | Description                                                |
+=====================+==================+==========+============================================================+
| Division Bit Widths | Comma-delimited  | 1,2,3,2  | The bit-width of output vectors                            |
|                     | Integers         |          |                                                            |
+---------------------+------------------+----------+------------------------------------------------------------+
| Radix Positions     | Comma-delimited  | 0,0,1,0  | The fixed-point radix bit-position of the output vectors   |
|                     | Integers         |          |                                                            |
+---------------------+------------------+----------+------------------------------------------------------------+
| Output Division     | Comma-delimited  | 2,1,0,0  | The cast-type of each output vector:                       |
| Types               | Integers {0,1,2} |          | (ufix=0, fix=1, bool=2)                                    |
+---------------------+------------------+----------+------------------------------------------------------------+

===========
Munge
===========
Reorders equal-slices of the input bus.

-----
Ports
-----
+-------------+-----------------+------------+-------------------------------------------------+
| Signal      | Type            | Size       | Description                                     |
+=============+=================+============+=================================================+
| din         | std_logic_vector| any        | The input vector                                |
+-------------+-----------------+------------+-------------------------------------------------+
| dout        | std_logic_vector| any        | The output vector                               |  
+-------------+-----------------+------------+-------------------------------------------------+

----------
Parameters
----------
+---------------------+------------------+----------+------------------------------------------------------------+
| Generic             | Type             | Value    | Description                                                |
+=====================+==================+==========+============================================================+
| Divisions           | Integer          | 4        | The number of equally-sized divisions of the input vector  |
+---------------------+------------------+----------+------------------------------------------------------------+
| Division Bit Width  | Integer          | 2        | The size of the divisions                                  |
+---------------------+------------------+----------+------------------------------------------------------------+
| Division Order      | Comma-delimited  | 3,0,2,1  | The order of division-indices that                         |
|                     | Integers         |          | determines the output vector                               |
+---------------------+------------------+----------+------------------------------------------------------------+