Misc Library

Purpose

The misc library contains all casper_misc HDL modules wrapped for Simulink. These misc blocks are essential to the design of most DSP.

Bit Reverse

Reverses the bit order of an unsigned input vector. Differs from the original CASPER block as it does not require the user to specify number of bits.

Ports

Signal	Type	Size	Description
in_val	std_logic_vector	any	The input vector to be reversed
out_val	std_logic_vector	any	The reversed input vector

Parameters

Generic	Type	Value	Description
Asynchronous operation	Boolean	False	If checked, the block will act in a combinatorial way. If unchecked, a registered way

Edge Detect

Detects the specified edge on the input signal synchronously. Output signal will then either be equal to the input signal if polarity is set ‘high’, or equal to zero’s if polarity is ‘low’.

Ports

Signal	Type	Size	Description
in_sig	std_logic_vector	any	The input signal on which you wish to detect an edge
out_sig	std_logic_vector	any	Output edge detection.

Parameters

Generic	Type	Value	Description
Edge Type	String	“rising”	Options are “rising”, “falling” or “both”.
Output polarity	String	“high”	Options are “high” or “low”.

Armed Trigger

Makes a boolean trigger signal armable.

Ports

Signal	Type	Size	Description
trig_in	std_logic	1	Trigger signal
arm	std_logic	1	Arm signal
trig_out	std_logic	1	Output boolean signal

Pulse Extender

Extend the high-duration of a pulse by a number of clock periods, from the rising edge.

Ports

Signal	Type	Size	Description
i_pulse	std_logic	1	The input pulse signal
o_pulse	std_logic	1	The output pulse signal

Parameters

Generic	Type	Value	Description
Pulse Extension	Integer	4	The clock-period length of the pulse’s high.

Real/Imaginary to Complex

An extension of the concatenation block that concatenates two equal width vectors to produce a single “complex” vector.

Ports

Signal	Type	Size	Description
re_in	std_logic_vector	equal to im_in’RANGE	The input real signal
im_in	std_logic_vector	equal to re_in’RANGE	The input imaginary signal
c_out	std_logic_vector	2*width(re_in)	The concatenation result

Parameters

Generic	Type	Value	Description
Asynchronous operation	Boolean	False	If checked, the block will act in a combinatorial way. If unchecked, a registered way

Complex to Real/Imaginary

This block performs a slice of g_bit_width to split a complex vector to produce a real and imaginary vector of length g_bit_width. Note that the bit_width supplied need not be half of the complex vector length which will cause an overlapping of bits in the real and imaginary vectors.

Ports

Signal	Type	Size	Description
c_in	std_logic_vector	any	The input complex signal
re_out	std_logic_vector	g_bit_width	A slice result from MSB downto MSB - g_bit_width
re_out	std_logic_vector	g_bit_width	A slice result from MSB - g_bit_width -1 downto 0

Parameters

Generic	Type	Value	Description
Asynchronous operation	Boolean	False	If checked, the block will act in a combinatorial way. If unchecked, a registered way
g_bit_width	Natural	8	Specifies the size of the re_in/im_in slices.

Complex to Real/Imaginary

Convert real and imaginary components of a complex input to the specified bit width and precision.

Ports

Signal	Type	Size	Description
din_in	std_logic_vector	any	The input complex signal
din_out	std_logic_vector	any	The output complex signal

Parameters

Generic	Type	Value	Description
bit_width_in	Natural	8	The input bit width of the real and imaginary components.
bin_point_in	Natural	0	The input binary point of the real and imaginary components.
bit_width_out	Natural	8	The output bit width of the real and imaginary components.
bin_point_out	Natural	0	The output binary point of the real and imaginary components.
quantization	String	“Round”	The rounding scheme used if bit_width_in > bit_width_out
clip	Boolean	FALSE	The overflow scheme used if bit_width_in > bit_width_out
latency	Natural	2	The required clock cycles the block needs to take

Freeze Counter

A freeze counter is an enabled counter which holds its final value (regardless of enables) until it is reset.

Ports

Signal	Type	Size	Description
en	std_logic	1	Counter enable
rst	std_logic	1	Module reset signal
addr	std_logic_vector	any	Counter value
we	std_logic	1	Write enable signal
done	std_logic	1	Counter has reached freeze point

Parameters

Generic	Type	Value	Description
num_cntr_bits	Natural	8	Value at which the counter will freeze = 2^num_cntr_bits

Stopwatch

A stopwatch is an stop/start counter which starts counting when start goes high and holds its final value after stop goes high until it is reset.

Ports

Signal	Type	Size	Description
reset	std_logic	1	Module reset signal
start	std_logic	1	Module start signal
stop	std_logic	1	Module stop signal
count	std_logic_vector	any	Counter value

Triggered Counter

A triggered counter is a counter starts counting at the rising edge of a trigger signal and counts up to run length -1. Valid signal goes low when counter has reached that value.

Ports

Signal	Type	Size	Description
trig	std_logic	1	Trigger to start counting
count	std_logic_vector	any	Counter value
valid	std_logic	1	Counter has reached maximum point and goes low

Parameters

Generic	Type	Value	Description
run_length	Natural	8	Maximum value - 1 counter will count to

Power

Squares real and imaginary components of complex input and adds them. Optionally can use fabric or DSP48.

Ports

Signal	Type	Size	Description
din	std_logic_vector	any	The input complex signal
dout	std_logic_vector	any	The output real power signal

Parameters

Generic	Type	Value	Description
bit_width_in	Natural	8	The input bit width of the real and imaginary components.
add_latency	Natural	2	The required clock cycles the block needs to take for addition
mult_latency	Natural	2	The required clock cycles the block needs to take for multiplication
Use DSP	Boolean	False	If checked, the block will use DSP48 chips for arithmetic

Complex Add Sub

Computes (a + b)/2 and (a - b)/2 respectively. This is unlike the original block and is works only within certain constraints as the desired behaviour is not clear. Total latency will = 2*add_latency.

Ports

Signal	Type	Size	Description
a	std_logic_vector	any	The input complex signal for a
b	std_logic_vector	any	The input complex signal for b
a+b	std_logic_vector	same as a and b	The sum (a + b)/2 complex result
a-b	std_logic_vector	same as a and b	The sum (a - b)/2 complex result

Parameters

Generic	Type	Value	Description
bit_width_in	Natural	8	The bit width of the separate real and imaginary components
add_latency	Natural	2	The required clock cycles taken for addition

Convert

Does not support upscaling number of fractional bits (eg 8_5 to 8_4 is ok, but not 8_4 to 8_5). Block is not producing the same results as the original block and requires some further debugging of the VHDL.

Ports

Signal	Type	Size	Description
din	std_logic_vector	any	The input vector to be converted signal
din	std_logic_vector	any	The output signal of type Fix(n_bits_out,bin_pt_out)

Parameters

Generic	Type	Value	Description
bin_pt_in	Natural	8	The input binary point of the signal
n_bits_out	Natural	7	The output bit width of the signal
bin_pt_out	Natural	8	The output binary point of the signal
quantization	String	“Round”	The rounding scheme used internally
overflow	Boolean	“Wrap”	The overflow scheme used internally
csp_latency	Natural	2	The required clock cycles the block needs to take for convert

Conv

Converts an (8-bit) unsigned number to 2’s complement. This block should eventually be able to handle arbitrary width inputs. Block produces the same results as the original block but cannot be verified in VHDL as it depends on the Simulink Fixpoint representation.

Ports

Signal	Type	Size	Description
din	std_logic_vector	8	The input vector to be converted signal
din	std_logic_vector	8	The output signal of type Fix(8,7)